A number of Eurotherm’s products are configured by wiring together device Function Blocks using a graphical block diagram editor. This feature allows the user to implement customised control strategies. Eurotherm’s configuration software normally saves the graphical layout associated with a given strategy. However, there are occasions where this layout information is not available. In these cases, a layout must be generated automatically when the user goes to edit/view the strategy. The aim of this project is to research algorithms for optimal layout of wiring diagrams, and to implement an appropriate algorithm within Eurotherm’s device configuration software.
Eurotherm are investigating the use of EtherCAT as a realtime Ethernet backplane. EtherCAT is an open standard extension to the Ethernet protocol and is fully compatible with 100Mbps Ethernet. It supports rapid low level messaging in sub 1ms intervals for fast realtime control. EtherCAT is based on a dedicated interface at the lowest hardware level which is available either as an ASIC, as an FPGA specific IP core or as source VHDL.
Eurotherm would like to investigate the source VHDL so that we may be independent of ASIC and IP core restrictions and obsolescence.
This project would take the source VHDL and implement it on either a Xilinx or Altera FPGA (or possibly both) interfacing to a simple backend device to demonstrate feasibility. Further consideration would need to be given to the implementation of communications redundancy.
The project will involve the use of VHDL development and simulation tools and the hardware design and construction of a suitable backend device. Some software design for the backend device firmware may be required.